As the critical dimensions of semiconductor devices continue to shrink, more precise processing is required to enable functional devices at smaller scales. For example, the inventors have discovered that structures, such as a vias, trenches, dual damascene structures, or other structures having high aspect ratios (e.g., a feature height to width ratio of greater than about 4:1) and/or critical dimensions of less than about 22 nm, are often not sufficiently metalized during conventional processing. For example, the inventors have discovered that methods such as physical vapor deposition or the like do not achieve adequate deposition of the metal on lower portions of the structure, such as bottom surfaces of a via or trench, causing voids or other defects in the structure. Such defects may result in failure of the device.
Accordingly, the inventors have provided improved methods of forming interconnect structures.